Chip package structure and method for forming chip package
US11232999B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Feb 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.