Fast bus inversion for non-volatile memory
US11237729B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Oct 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An inversion encoder is configured to receive a plurality of bytes of data for parallel output to a data bus; determine, in parallel, Hamming distances of neighboring pairs of bytes of the received plurality of bytes of data; for each neighboring pair of bytes of the received plurality of bytes, determine, in parallel, for each of the neighboring pairs of bytes, whether a respective Hamming distance satisfies a majority function; if a respective Hamming distance for a particular pair of bytes of the neighboring pairs of bytes satisfies the majority function: set an inversion bit for a second byte of the particular pair of bytes to be the opposite of an inversion bit for a first byte of the particular pair of bytes; invert, or forgo inverting, the second byte based on the inversion bit for the second byte; and provide the second byte for output to the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.