Semiconductor inspection and metrology systems for distributing job among the CPUs or GPUs based on logical image processing boundaries
US11237872B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2018 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.