Using embedded switches for reducing capacitive loading on a memory system
US11238904B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells and a second set of memory cells; a first group of switches, each including: a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode; a second group of switches, each including: a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode; and a third group of switches, each including: a first electrode connected to a first global bit line, and a second electrode connected to the second electrodes of the first group of switches and the second electrodes of the second group of switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.