Patent · US Active

Planar slab vias for integrated circuit interconnects

US11239156B2 · kind B2 · utility

3Cited by

4References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Elijah V. Karpov · Portland, US
Manish Chandhok · Beaverton, US
Nafees Kabir · Portland, US

Key dates

Filing date	Mar 19, 2020
Grant date	Feb 1, 2022
Priority date	—
Expiry date	Mar 19, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76883
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.