Inventor · Portland, OR, US

Nafees Kabir

23Patents
2h-index
56Co-inventors
52Inventor score

Filing activity: Jun 28, 2018 → Oct 20, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11444024B2 Subtractively patterned interconnect structures for integrated circuits Electricity 4 Active
US11239156B2 Planar slab vias for integrated circuit interconnects Electricity 3 Active
US10665499B2 Integrated circuit with airgaps to control capacitance Electricity 2 Active
US11289421B2 Methods and structures for improved electrical contact between bonded integrated circuit interfaces Electricity 1 Active
US11462469B2 Single mask lithography line end enhancement Electricity 1 Active
US11784123B2 Methods and structures for improved electrical contact between bonded integrated circuit interfaces Electricity 0 Active
US11837644B2 Contact over active gate structures with metal oxide-caped contacts to inhibit shorting Electricity 0 Active
US12266729B2 Angled etch to enable tin removal from selected sidewalls Electricity 0 Active
US12341092B2 Planar slab vias for integrated circuit interconnects Electricity 0 Active
US11404307B2 Interconnect structures and methods of fabrication Electricity 0 Active
US12087836B2 Contact over active gate structures with metal oxide-caped contacts to inhibit shorting Electricity 0 Active
US12261114B2 Metallization stacks with self-aligned staggered metal lines Electricity 0 Active
US11404482B2 Self-aligned repeatedly stackable 3D vertical RRAM Electricity 0 Active
US11424160B2 Self-aligned local interconnects Electricity 0 Active
US12412838B2 Integrated circuit structure with filled recesses Electricity 0 Active
US11887887B2 Interconnect structures and methods of fabrication Electricity 0 Active
US12027458B2 Subtractively patterned interconnect structures for integrated circuits Electricity 0 Active
US12293913B1 Directed self-assembly enabled subtractive metal patterning Electricity 0 Active
US11646266B2 Helmet structures for semiconductor interconnects Electricity 0 Active
US12266527B1 Directed self-assembly enabled patterning over metal layers using assisting features Electricity 0 Active
US11610810B2 Maskless air gap enabled by a single damascene process Electricity 0 Active
US11342227B2 Stacked transistor structures with asymmetrical terminal interconnects Electricity 0 Active
US11594673B2 Two terminal spin orbit memory devices and methods of fabrication Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.