Method of forming thin layers and method of manufacturing a non-volatile memory device using the same
US11239251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Apr 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.