Structure of memory device and fabrication method thereof
US11239419B2 · kind B2 · utility
0Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2019 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/841
Abstract
The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.