Patent · US Active

Master-slave D flip-flop

US11239830B2 · kind B2 · utility

1Cited by

3References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kuenemund · Munich, DE
Anton Huber · Burghausen, DE

Key dates

Filing date	Mar 11, 2021
Grant date	Feb 1, 2022
Priority date	—
Expiry date	Mar 11, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/35625
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.