System and method for scheduling instructions in a multithread SIMD architecture with a fixed number of registers
US11243904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Mar 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.