Semiconductor packages
US11244894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Mar 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.