Multi-division staircase structure of three-dimensional memory device and method for forming the same
US11244957B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Embodiments of structure and methods for forming a staircase structure of a memory device are disclosed. In an example, a memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs each has a first number of divisions at different depths along a first direction. The plurality of stairs extend along a second direction perpendicular to the first direction. Each of the first number of divisions of a respective stair includes a conductor portion on the top surface of the respective division and a second number of non-conductor portions under the conductor portion. The conductor portion and the non-conductor portions are insulated from one another by one or more dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.