Vertical multi-gate thin film transistors

US11245038B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Yih Wang · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Sean T. Ma · Portland, US
• Van Hoa Lee · Four Oaks, US

Key dates

• Filing date: Mar 30, 2017
• Grant date: Feb 8, 2022
• Expiry date: Feb 26, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/60

Abstract

Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).