Memory device resilient to cyber-attacks and malfunction
US11249689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Oct 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.