Stephan Rosner
45Patents
7h-index
37Co-inventors
69Inventor score
Filing activity: Jun 5, 2000 → Apr 25, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7313104B1 | Wireless computer system with latency masking | Electricity | 34 | Expired |
| US7729382B2 | Wireless computer system with queue and scheduler | Electricity | 16 | Active |
| US7149213B1 | Wireless computer system with queue and scheduler | Electricity | 15 | Expired |
| US9142215B2 | Power-efficient voice activation | Physics | 15 | Active |
| US10809944B1 | Memory device resilient to cyber-attacks and malfunction | Physics | 8 | Active |
| US7813459B2 | Digital data transfer between different clock domains | Electricity | 7 | Active |
| US10868679B1 | Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems | Electricity | 7 | Active |
| US7644226B1 | System and method for maintaining RAM command timing across phase-shifted time domains | Physics | 6 | Active |
| US6718356B1 | In-place operation method and apparatus for minimizing the memory of radix-r FFTs using maximum throughput butterflies | Physics | 5 | Expired |
| US8140778B1 | Apparatus and method for data capture using a read preamble | Physics | 4 | Active |
| US7404026B2 | Multi media card with high storage capacity | Physics | 3 | Active |
| US8700830B2 | Memory buffering system that improves read/write performance and provides low latency for mobile systems | Physics | 3 | Active |
| US11562781B1 | Memory devices with low pin count interfaces, and corresponding methods and systems | Physics | 3 | Active |
| US8230154B2 | Fully associative banking for memory | Physics | 3 | Active |
| US11411747B2 | Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems | Electricity | 2 | Active |
| US10552145B2 | Memory devices, systems, and methods for updating firmware with single memory device | Physics | 2 | Active |
| US7047328B1 | Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers | Physics | 2 | Expired |
| US9785613B2 | Acoustic processing unit interface for determining senone scores using a greater clock frequency than that corresponding to received audio | Physics | 2 | Active |
| US11030128B2 | Multi-ported nonvolatile memory device with bank allocation and related systems and methods | Emerging Cross-Sectional Technologies | 2 | Active |
| US8359423B2 | Using LPDDR1 bus as transport layer to communicate to flash | Physics | 2 | Active |
| US9477617B2 | Memory buffering system that improves read/write performance and provides low latency for mobile systems | Physics | 2 | Active |
| US7840900B1 | Replacing reset pin in buses while guaranteeing system recovery | Physics | 1 | Active |
| US11249689B2 | Memory device resilient to cyber-attacks and malfunction | Physics | 1 | Active |
| US9047237B2 | Power savings apparatus and method for memory device using delay locked loop | Emerging Cross-Sectional Technologies | 1 | Active |
| US11061663B2 | Memory devices, systems, and methods for updating firmware with single memory device | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.