High performance merge sort with scalable parallelization and full-throughput reduction
US11249720B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Nov 19, 2019 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Feb 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.