Self aligned gratings for tight pitch interconnects and methods of fabrication

US11251117B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Manish Chandhok · Beaverton, US
• Leonard P. GULER · Hillsboro, US
• Paul A. Nyhus · Portland, US
• Gobind Bisht · Irvine, US
• Jonathan Laib · Portland, US
• David Shykind · Buxton, US
• Gurpreet Singh · Alwar, IN
• Eungnak Han · Portland, US
• Noriyuki Sato · Hillsboro, US
• Charles H. Wallace · Portland, US
• Jinnie Aloysius · Portland, US

Key dates

• Filing date: Sep 5, 2019
• Grant date: Feb 15, 2022
• Expiry date: Sep 5, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.