Patent · US Active

Three-dimensional memory device without gate line slits and method for forming the same

US11251195B2 · kind B2 · utility

2Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 31, 2019
Grant dateFeb 15, 2022
Priority date
Expiry dateOct 31, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.