Processing system with a main processor pipeline and a co-processor pipeline
US11256516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2018 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a data memory, a first processor with first execution pipeline, and a co-processor with second execution pipeline branching from the first pipeline via an inter-processor interface. The first pipeline can decode instructions from an instruction set comprising first and second instruction subsets. The first subset comprises a load instruction which loads data from the memory into a register file, and a compute instruction of a first type which performs a compute operation on such loaded data. The second subset includes a compute instruction of a second type which does not require a separate load instruction to first load data from memory into a register file, but instead reads data from the memory directly and performs a compute operation on that data, this reading being performed in a pipeline stage of the second pipeline that is aligned with the memory access stage of the first pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.