Test circuit, memory device, storage device, and method of operating the same
US11257559B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Jan 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein may be a test circuit, a memory device, a storage device, and a method of operating the same. The word line test circuit may include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to, in response to the plurality of operation signals, generate a target voltage based on a test current, in which a current of a target word line varying with a test voltage is reflected, and to generate a comparison signal based on a result of a comparison between the target voltage and a reference voltage, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, cycles of which are counted until a level of the comparison signal changes from a first level to a second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.