Semiconductor structure and manufacturing method thereof
US11257668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate includes a first region and a second region; forming a first polycrystalline silicon layer on the substrate, wherein the first polycrystalline silicon layer covers the first region and the second region; forming a stacked structure on the first polycrystalline silicon layer; forming a protective layer on the stacked structure; forming a patterned photoresist layer on the protective layer, wherein the patterned photoresist layer exposes the protective layer in the second region; removing the protective layer and the stacked structure in the second region to expose the first polycrystalline silicon layer in the second region; removing the patterned photoresist layer; and forming a second polycrystalline silicon layer on the protective layer in the first region and the first polycrystalline silicon layer in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.