Interconnect structure and method for manufacturing the interconnect structure
US11257753B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | May 27, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | May 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76855
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.