Memory device and manufacturing method thereof
US11257833B2 · kind B2 · utility
0Cited by
39References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2019 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Sep 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.