Semiconductor element having an enhancement-type transistor structure

US11257915B2 · kind B2 · utility

Assignee

• Institut für Mikroelektronik Stuttgart · DE

Inventors

• Joachim Norbert Burghartz · Shrub Oak, US
• Mohammed Alomari · Stuttgart, DE
• Muhammad Alshahed · Stuttgart, DE

Key dates

• Filing date: May 6, 2020
• Grant date: Feb 22, 2022
• Expiry date: May 6, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

A semiconductor element includes an enhancement-type transistor structure with a layer construction including a base substrate, a first semiconductor layer, and a second semiconductor layer, which are arranged one on top of the other along a first direction. The transistor structure further has a source electrode, a gate electrode, and a drain electrode, which are spaced apart from one another along a second direction that is transverse to the first direction. The first and second semiconductor layers are formed by different group III nitride materials, such that a 2D electron gas forms in a boundary region of the first and second semiconductor layers. The first and second semiconductor layers have holes in the region of the gate electrode, between which holes multiple fins including the group III nitride materials remain. The gate electrode has a plurality of gate fingers extending into the holes.