High electron mobility transistor with doped semiconductor region in gate structure
US11257941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Apr 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.