No-enable setup clock gater based on pulse
US11258446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Apr 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/284
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.