Patent · US Active

Low-latency signaling-link retimer

US11258696B1 · kind B1 · utility

1Cited by

1References

18Claims

0Family size

Assignee

Asiera Labs, Inc. · US

Inventors

Casey Morrison · San Jose, US
Enrique Musoll · San Jose, US
Jitendra Mohan · Palo Alto, US
Pulkit Khandelwal · Cupertino, US
Subbarao Arumilli · Cupertino, US
Vikas Khandelwal · San Jose, US
Ken (Keqin) Han · Fremont, US
Charan Enugala · Newark, US
Vivek Trivedi · Fremont, US
Chi Feng · San Jose, US

Key dates

Filing date	Jun 4, 2020
Grant date	Feb 22, 2022
Priority date	—
Expiry date	Jun 4, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH04L69/28
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.