Apparatuses, systems, and methods for error correction
US11263078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Mar 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.