Memory component with a virtualized bus and internal logic to perform a machine learning operation
US11263156B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Oct 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component can include memory cells with a memory region to store a machine learning model and input data and another memory region to store host data from a host system. The memory component can include an in-memory logic, coupled to the memory cells, to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and can provide the additional data to the other memory region or the in-memory logic based on a characteristic of the additional data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.