Operating method of generating enhanced bit line voltage and non-volatile memory device
US11264091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Oct 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.