Spacer structure for semiconductor device
US11264485B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Dec 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
Abstract
The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.