Device, method and system for promoting channel stress in a NMOS transistor
US11264501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.