Symmetrically-interconnected tunable time delay circuit
US11264976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Jun 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.