Interconnected memory grid with bypassable units
US11269526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Sep 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.