Inventor · Ramat Gan, IL

Elad RAZ

22Patents
1h-index
14Co-inventors
46Inventor score

Filing activity: Aug 2, 2018 → Nov 3, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11113059B1 Dynamic allocation of executable code for multi-architecture heterogeneous computing Physics 2 Active
US11720496B2 Reconfigurable cache architecture and methods for cache coherency Physics 1 Active
US11176041B2 Reconfigurable cache architecture and methods for cache coherency Physics 1 Active
US11875153B1 Executing concurrent threads on a reconfigurable processing grid Physics 1 Active
US12340221B2 Executing concurrent threads on a reconfigurable processing grid Physics 0 Active
US11269526B2 Interconnected memory grid with bypassable units Physics 0 Active
US12197919B1 Dynamic software interface translation for computing in a heterogeneous environment Physics 0 Active
US11644990B2 Interconnected memory grid with bypassable units Physics 0 Active
US10817309B2 Runtime optimization of configurable hardware Emerging Cross-Sectional Technologies 0 Active
US11720491B2 System and method for sharing a cache line between non-contiguous memory areas Physics 0 Active
US12020069B2 Memory management in a multi-processor environment Physics 0 Active
US11995419B1 Graphical user interface for code to dataflow graph representation Physics 0 Active
US12189412B2 Dynamic allocation of executable code for multi-architecture heterogeneous computing Physics 0 Active
US11294686B1 Optimizing reconfigurable hardware using data sampling Physics 0 Active
US12360902B2 Reconfigurable cache architecture and methods for cache coherency Physics 0 Active
US11966619B2 Background processing during remote memory access Physics 0 Active
US12333231B1 Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof Physics 0 Active
US10817344B2 Directed and interconnected grid dataflow architecture Electricity 0 Active
US12130736B2 System and method for sharing a cache line between non-contiguous memory areas Physics 0 Active
US11144238B1 Background processing during remote memory access Physics 0 Active
US12056376B2 Interconnected memory grid with bypassable units Physics 0 Active
US11630669B2 Dynamic allocation of executable code for multiarchitecture heterogeneous computing Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.