System idle time reduction methods and apparatus
US11269555B2 · kind B2 · utility
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4References
20Claims
0Family size
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Key dates
| Filing date | Jun 22, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jun 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.