Memory-based distributed processor architecture
US11269743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2019 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jul 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2015/765
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.