Elad Sity
24Patents
3h-index
12Co-inventors
56Inventor score
Filing activity: May 23, 2013 → Jan 8, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9870016B2 | Circuit for interconnected direct current power sources | Emerging Cross-Sectional Technologies | 8 | Active |
| US10664438B2 | Memory-based distributed processor architecture | Physics | 5 | Active |
| US10705551B2 | Circuit for interconnected direct current power sources | Emerging Cross-Sectional Technologies | 4 | Active |
| US11334104B2 | Circuit for interconnected direct current power sources | Emerging Cross-Sectional Technologies | 1 | Active |
| US10885951B2 | Memory-based distributed processor architecture | Physics | 1 | Active |
| US11023336B2 | Memory-based distributed processor architecture | Physics | 1 | Active |
| US12204474B2 | Communications for computational memory modules | Physics | 0 | Active |
| US12038838B2 | Distributed processor memory chip with multi-port processor subunits | Physics | 0 | Active |
| US12277076B2 | Error correction for computational memory modules | Physics | 0 | Active |
| US12242381B2 | In-memory zero value detection | Physics | 0 | Active |
| US11126511B2 | Memory-based distributed processor architecture | Physics | 0 | Active |
| US12306653B2 | Circuit for interconnected direct current power sources | Emerging Cross-Sectional Technologies | 0 | Active |
| US12242478B2 | Data analysis acceleration architecture | Physics | 0 | Active |
| US11860782B2 | Compensating for DRAM activation penalties | Physics | 0 | Active |
| US11301340B2 | Memory-based distributed processor architecture | Physics | 0 | Active |
| US11740647B2 | Circuit for interconnected direct current power sources | Emerging Cross-Sectional Technologies | 0 | Active |
| US11914487B2 | Memory-based distributed processor architecture | Physics | 0 | Active |
| US11514996B2 | Memory-based processors | Physics | 0 | Active |
| US11901026B2 | Partial refresh | Physics | 0 | Active |
| US12405866B2 | High performance processor for low-way and high-latency memory instances | Physics | 0 | Active |
| US11269743B2 | Memory-based distributed processor architecture | Physics | 0 | Active |
| US11837305B2 | Memory-based logic testing | Physics | 0 | Active |
| US10762034B2 | Memory-based distributed processor architecture | Physics | 0 | Active |
| US11817167B2 | Variable word length access | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.