Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
US11270994B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Aug 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over the work function layer. The barrier layer is sandwiched between the metal layer and the work function layer. The barrier layer includes silicon or aluminum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.