Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)

US11271011B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Shyam Agarwal · Mado-myeon, KR
• Abhishek Ghosh · Bengaluru, IN
• Parvinder Kumar Rana · Bengaluru, IN

Key dates

• Filing date: Jul 9, 2020
• Grant date: Mar 8, 2022
• Expiry date: Jul 9, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/931

Abstract

Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.