Via resistance reduction
US11271042B2 · kind B2 · utility
0Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2018 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/231
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.