Systems and methods for junction termination in semiconductor devices

US11271076B2 · kind B2 · utility

Assignee

• General Electric Company · US

Inventors

• Stephen Daley Arthur · Glenville, US
• Victor Torres · Clifton Park, US
• Michael J. Hartig · Austin, US
• Reza Ghandi · Niskayuna, US
• David Alan Lilienfeld · Niskayuna, US
• Alexander Viktorovich Bolotnikov · Niskayuna, US

Key dates

• Filing date: Jul 19, 2019
• Grant date: Mar 8, 2022
• Expiry date: Sep 29, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.