Integrated circuit
US11271150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jun 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.