Profile and queue-based wear leveling of memory devices
US11275680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.