Memory device including a plurality of area having different refresh periods, memory controller controlling the same and memory system including the same
US11276452B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Aug 7, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Aug 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.