Memory with partial array refresh
US11276454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Jul 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.