Semiconductor package
US11276632B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.