Stress mitigation structure
US11276650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.