Vertical memory devices and methods of manufacturing the same
US11276706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | May 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.