Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA
US11277135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Nov 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.